1. Field of the Invention
The present invention relates to a processing circuit, a method for the same, and an image processor, more particularly relates to a processing circuit, a method for the same, and an image processor improved a speed of the processing including a logarithm of 2 operations and a reduction of scale of the hardware.
2. Description of the Related Art
Computer graphics are often used in a variety of computer aided design (CAD) systems and amusement machines. Especially, along with the recent advances in image processing techniques, systems using three-dimensional computer graphics are becoming rapidly widespread.
In three-dimensional computer graphics, the color value of each pixel is calculated at the time of deciding the color of each corresponding pixel. Then, rendering is performed for writing the calculated value to an address of a display buffer (frame buffer) corresponding to the pixel.
One of the rendering methods is polygon rendering. In this method, a three-dimensional model is expressed as a composite of triangular unit graphics (polygons). By drawing the polygons as units, the colors of the pixels of the display screen are decided.
In the polygon rendering, processing is performed for interpolation inside a triangle by the coordinates (x, y, z), color data (R, G, B), homogeneous coordinates (s, t) of texture data indicating an image pattern for pasting, and the value of a homogeneous term g for vertexes of the triangle in a physical coordinate system.
Here, simply speaking, the homogeneous term g is like an enlargement and reduction rate. The coordinates in a UV coordinate system of an actual texture buffer, that is, the texture coordinate data (U, V), correspond to the (s/q, t/q)=(u, v) obtained by dividing the homogeneous coordinates (s, t) by the homogeneous term g multiplied by the texture sizes USIZE and VSIZE.
In a three-dimensional computer graphic system using such polygon rendering, when drawing, a texture mapping is performed to read texture data having the optimum reduction rate from the texture buffer storing a plurality of texture data corresponding to different reduction rates, pasting this read texture data to the surface of the 3D model in units of pixels, and thereby obtaining image data with a high reality.
At this time, the reduction rate of the texture data to be read is determined in for example pixel units.
Summarizing the problem to be solved by the invention, in the three dimensional computer graphic system as mentioned above, how the reduction rate of the texture data to be read from the texture buffer is determined for each pixel is important for achieving a higher quality of the display image and a reduction of the scale.
An object of the present invention is to provide a processing circuit which can be used in an image processor such as a three-dimensional computer graphic system and other hardware and can realize processing including logarithm of 2 operations by a small sized circuit configuration.
Another object of the present invention is to provide an image processor capable of displaying a high quality image with a small size hardware configuration.
Still another object of the present invention is to provide a processing method capable of performing processing at a high speed.
To achieve the first object, according to a first aspect of the present invention, there is provided a processing circuit for performing the operation shown in the following equation (1)
M=log2q+maxe xe2x80x83xe2x80x83(1) 
using binary data g having an integer part and a decimal part and data maxe comprised by only an integer part, comprising a normalization circuit for normalizing the data g to generate an exponent ge and a mantissa gm, a data outputting means for receiving as its input the mantissa gm and outputting data xcexc indicating xe2x80x9clog2({1, qm})xe2x88x92qmxe2x80x9d where {1, qm} indicates a bit coupling where xe2x80x9c1xe2x80x9d is the integer part and xe2x80x9cqmxe2x80x9d is the decimal part, and an adder circuit for adding data obtained by bit coupling of the data ge and the gm and data obtained by bit coupling of the data maxe and the data xcexc.
That is , in the processing circuit of the first aspect of the present invention, the normalization circuit normalizes the data g to generate the exponent ge and the manitssa gm.
Next, it outputs the mantissa gm to the data outputting means. The data outputting means obtains the data xcexc indicating xe2x80x9clog2({1, qm})xe2x88x92qmxe2x80x9d corresponding to the mantissa gm and outputs the data xcexc.
Next, the adder circuit adds the data obtained by bit coupling of the data ge and gm and the data obtained by bit coupling of the data maxe and the data xcexc to calculate data M.
The processing circuit of the first aspect of the present invention utilizes the fact that the data xcexc is comprised by only the decimal part since log2({1, qm}) and the data gm are similar, bit couples the data maxe comprised by only the integer part and the data xcexc, and thus realizes addition of the data maxe. For this reason, the addition using the adder circuit can be reduced, and a reduction of the size and the increase of the speed can be achieved.
In the processing circuit of the first aspect of the present invention, preferably the data outputting means has a correspondence table between the mantissa gm and the xcexc data, acquires the data xcexc corresponding to an input mantissa gm by using the correspondence table, and outputs the related obtained data xcexc.
Further, in the processing circuit of the first aspect of the present invention, preferably the data outputting means has a program for receiving as input the mantissa gm and generating the xcexc data and performs processing based on the related program to acquire the data xcexc corresponding to an nput mantissa gm and output the related acquired data xcexc.
To achieve the first object, according to a second aspect of the present invention, there is provided a processing circuit for calculating data LOD by performing the operation shown in the following equation (2).
LOD=Clamp (((log121/q)+maxe) less than  less than L+K) xe2x80x83xe2x80x83(2) 
using binary data g having an integer part and a decimal part, data maxe comprised by only an integer part, and data L and K, comprising a normalization circuit for normalizing the data g to generate an exponent ge and a mantissa gm, a first shift circuit for shifting the data obtained by bit coupling of the data ge and the gm toward the most significant bit (MSB) by exactly a value indicated by the data L, a first inversion circuit for inverting the output of the first shift circuit, a data outputting means for receiving as its input the mantissa gm and outputting data xcexc indicating xe2x80x9clog2({1, qm})xe2x88x92qmxe2x80x9d where {1, qm} indicates a bit coupling where xe2x80x9c1xe2x80x9d is the integer part and xe2x80x9cqmxe2x80x9d is the decimal part, a second shift circuit for shifting the data obtained by bit coupling of the data maxe and the data xcexc toward the MSB by exactly the value indicated by the data L, a second inversion circuit for inverting the output of the second shift circuit, an adder circuit for adding the data obtained by bit coupling of the data K and the binary number xe2x80x9c10xe2x80x9d, an adder circuit for adding the output of the first shaft circuit and the output of the second shift circuit, and a clamp circuit for clamping the output of the adder circuit to a predetermined number of bits to generate the data LOD.
That is, in the processing circuit of the second aspect of the present invention, the normalization circuit normalizes the data g to generate the exponent ge and the mantissa gm.
Then, the data obtained by bit coupling of the data ge and gm is output to the first shaft circuit. The first shift circuit shifts the related data toward the MSB by exactly the value indicated by the data L.
Next, the first inversion circuit inverts the output of the first shift circuit.
Further, the data outputting means receives as input the mantissa gm and outputs the data xcexc indicatingxe2x80x9clog2({1, qm})xe2x88x92qmxe2x80x9d corresponding to the mantissa gm.
Then, the second shift circuit shirts the data obtained by bit coupling of the data maxe and the data xcexc toward the MSB by exactly the value indicated by the data L.
Next, the second inversion circuit inverts the output of the second shift circuit.
Then, the adder circuit adds the data obtained by bit coupling of the data K and the binary number xe2x80x9c10xe2x80x9d, the output of the first shift circuit, and the output of the second shift circuit.
Next, the clamp circuit clamps the output of the adder circuit to a predetermined number of bits to generate the data LOD.
The processing circuit of the second aspect of the present invention utilizes the fact that the data xcexc is comprised by only the decimal part since log2({1, qm}) and the data gm are similar, bit couples the data maxe comprised by only the integer part and the data xcexc, and thus realizes addition of the data maxe. For this reason, the addition using the adder circuit can be reduced, and a reduction of the size and the increase of the speed can be achieved.
To achieve the second object, according to a third aspect of the present invention, there is provided a image processor for expressing a 3D model by a combination of a plurality of unit graphics to which common processing conditions apply, determining a reduction rate from homogeneous coordinates (s, t) and a homogeneous term g contained in the image data for each pixel, and linking texture data according to the related determined reduction rate with the unit graphics, comprising a storing means storing a plurality of texture data corresponding to different reduction rates, a representative point determining circuit for determining a pixel forming a representative point from among pixels located inside a unit graphic to be processed among a plurality of pixels to be simultaneously processed, a reduction rate calculation circuit for calculating a reduction rate LOD from the following equation (3)
LOD=Clamp (((log21/q)+maxe) less than  less than L+K) xe2x80x83xe2x80x83(3) 
using data maxe comprised by only an integer part indicating a maximum exponent of homogeneous coordinates (s, t) of the vertexes of a unit graphic being processed and the homogeneous term g, the homogeneous term g having an integer part and a decimal part corresponding to the determining representative point, and the data L and K, and a reading circuit for reading texture data from the storing means by using the calculated reduction rate LOD, wherein the reduction rate calculation circuit has a normalization circuit for normalizing the data g to generate an exponent ge and a mantissa gm, a first shift circuit for shifting the data obtained by bit coupling of the data ge and the gm toward the MSB by exactly the value indicated by the data L, a first inversion circuit for inverting the output of the first shift circuit, a data outputting means for receiving as its input the mantissa gm and outputting data xcexc indicating xe2x80x9clog2({1, qm})xe2x88x92qmxe2x80x9d where {1, qm} indicates a bit coupling where xe2x80x9c1xe2x80x9d is the integer part and xe2x80x9cqmxe2x80x9d is the decimal part, a second shift circuit for shifting the data obtained by bit coupling of the data maxe and the data xcexc toward the MSB by exactly the value indicated by the data L, a second inversion circuit for inverting the output of the second shift circuit, and adder circuit for adding the data obtained by bit coupling of the data K and the binary number xe2x80x9c10xe2x80x9d, an adder circuit for adding the output of the first shift circuit and the output of the second shift circuit, and a clamp circuit for clamping the output of the adder circuit to a predetermined number of bits to generate the data LOD.
That is, in the image processor of the third aspect according to the present invention, the representative point determining circuit determines the pixel forming the representative point from among the pixels located inside a unit graphic to be processed among a plurality of pixels to be processed at the same time.
Next, the reduction rate calculation circuit calculates the reduction rate LOD from the above equation (3) using the data maxe comprised by only an integer part indicating the maximum exponent of homogeneous coordinates (s, t) of the vertexes of the unit graphic being processed and the homogeneous term g, the homogeneous term g having an integer part and a decimal part corresponding to the determined representative point, and the data L and K,
The mode of operation of the reduction rate calculation in the related reduction rate calculation circuit is the same as that in the processing circuit of the second aspect of the present invention.
Next, the reading circuit reads the texture data from the storing means by using the calculated reduction rate LOD.
According to a fourth aspect of the present invention, there is provided an image processor for expressing a 3D model by a combination of a plurality of unit graphics to which common processing conditions apply, determining a reduction rate from homogeneous coordinates (s, t) and a homogeneous term g contained in the image data for each pixel, and linking texture data according to the related determined reduction rate with the unit graphics, comprising a storing means storing a plurality of texture data corresponding to different reduction rates, a representative point determining circuit for determining a pixel forming a representative point from among pixels located inside a unit graphic to be processed among a plurality of pixels to be simultaneously processed, a reduction rate calculation circuit for calculating a reduction rate LOD from the following equation (4)
LOD+Clamp (((log21/q)+maxe) less than  less than L+K) xe2x80x83xe2x80x83(4) 
using data maxe comprised by only an integer part indicating a maximum exponent of homogeneous coordinates (s, t) of the vertexes of a unit graphic being processed and the homogeneous term g, the homogeneous term g having an integer part and a decimal part corresponding to the determined representative point, and the data L and K, and a reading circuit for reading texture data from the storing means by using the calculated reduction rate LOD, wherein the reduction rate calculation circuit has a normalization circuit for normalizing the data g to generate an exponent ge and a mantissa gm, a data outputting means for receiving as its input the mantissa gm and outputting data b indicating xe2x80x9clog2({1, qm})xe2x80x9d where {1, qm} indicates a bit coupling where xe2x80x9c1xe2x80x9d is the integer part and xe2x80x9cqmxe2x80x9d is the decimal part, a first inversion circuit for inverting the data obtained by bit coupling of the data ge and the data b, a second inversion circuit for inverting the data maxe, a first adder circuit for adding the binary number data xe2x80x9c10xe2x80x9d, the output of the first inversion circuit, and the output of the second inversion circuit, a shift circuit for shifting the output of the first adder circuit toward the MSB by exactly the value indicating by the data L, a second adder circuit for adding the output of the shift circuit and the data K, and a clamp circuit for clamping the output of the adder circuit to a predetermined number of bits to generate the data LOD.
That is, in the image processor of the fourth aspect according to the present invention, the reduction rate calculation circuit calculates the reduction rate LOD as indicated below.
Namely, the normalization circuit normalizes the data g to generate the exponent ge and the mantissa gm.
Then, the data outputting means receives as its input the mantissa gm and outputs the data b indicating xe2x80x9clog2({1, qm})xe2x80x9d.
Next, the first inversion circuit inverts the data obtained by bit coupling of the data ge and the data b.
Further, the second inversion circuit inverts the data maxe.
Next, the first adder circuit adds the binary data xe2x80x9c10xe2x80x9d, the output of the first inversion circuit, and the output of the second inversion circuit.
Then, the shift circuit shifts the output of the first adder circuit toward the MSB by exactly the value indicated by the data L.
Next, the second adder circuit adds the output of the first shift circuit and the data K.
Next, the clamp circuit clamps the output of the second adder circuit to a predetermined number of bits to generate the reduction rate LOD.
To achieve the third object, according to a fifth aspect of the present invention, there is provided a processing method for performing the operation shown in the following equation (5)
M=log2q+maxe xe2x80x83xe2x80x83(5) 
using binary data g having an integer part and a decimal part and data maxe comprised by only an integer part, comprising normalizing the data g to generate an exponent ge and a mantissa gm, acquiring data xcexc indicating xe2x80x9clog2({1, qm})xe2x88x92qmxe2x80x9d, where {1, qm} indicates a bit coupling where xe2x80x9c1xe2x80x9d is the integer part and xe2x80x9cqmxe2x80x9d is the decimal part, corresponding to the mantissa gm by using a correspondence table between the mantissa gm and the data xcexc or a program for generating the data xcexc by inputting the mantissa gm, and adding the data obtained by bit coupling of the data ge and gm and the data obtained by bit coupling of the data maxe and the data xcexc to calculate the data M.